|I/O Port (Hex)||Function||I/O bit(s)|
|00 - 7D||Not used|
|80 - E7||Not used|
|E8 - EA||Floppy disk interface|
|EB - EF||Not used|
|F0 - F7|| Reserved for use in the |
entertainment module for
addressing the sound-
generation chip and the
|F8 - FB||Not used|
|FC|| Cassette and sound |
Cassette port input
| D0 (write)|
|FD|| CP/M mode memory mapper|
Vertical sync signal
| D0 (write)|
|FE|| 1200 bps serial printer|
Clear to send status
|FF|| Software lock pattern|
The format employed is very similar to conventional similar to conventional serial interface format. One data byte on cassette consists of one start bit of 0, 8 data bits and 2 stop bits of 1. A mark is represented by 2 full cycles of square wave with perion 0.6mS, a space also has 2 cycles but with a period of 1.2mS. In cassette interface one has to minimize problems due to DC offset thus square wave pattern was chosen. Prior to any data block transfer a group of sync bytes are sent for data recovery synchronization. In BASIC there are 16 sync bytes of 0xFF and there must be 6 consecutive sync bytes to be read back for sync verification.
|<-mark 2*.6mS->|<- space 2*1.2mS ->|
+++++ +++++ ++++++++ ++++++++ +++
+ + + + + + + + +
+ + + + + + + + +
++++++ +++++ +++++ ++++++++ ++++++++
To read stored data from cassette the program should look at bit zero of the cassette input port and measure the time difference between leading edges or trailing edges. This is to prevent DC level shifting from altering pulse width of data. The program should then look for sync bytes for data synchronisation before data block transfer. If there is any task that must be performed during cassette loading, the maximum allowable time to do the job after one byte from cassette, must be less than 80% of the period of a mark cycle. Control must be returned at that time to the cassette routine in order to maintain data integrity.
Sound and cassette port use a common pin. Therefor the signal to cassette will appear on audio output. Sound port is a simple one bij I/O and therefor it must be toggled at a specific rate under software control.
Bit D0 of this port controls the swapping of the lower 16K block in the memory map with the upper 16K. A 1 in this bit indicates swapping. This bit is reset after power up initialization.
The current state of the vertical sync will appear on bit 0 during a read of this port. The waveform and timing spec is shown as follows:
|<- Active scan period ->|V.sync |<-
| 12.8 mS |3.6 for PAL
| |2.8 for NTSC
+ + +
+ + +
This is a single bit I/O at D0, it will perform as a serial output port under software control. Since timing is done by software therefore the baudrate is variable. In BASIC this is a 1200 baud printer port for the 40 column thermal printer.
The printer output is initialized to logical zero by hardware reset. Therefor it must be written with a one under software control after powre on reset.
Port 0xFE when read, presents the clear to send status from PRNHASK pin at bit D0. A 1 indicates printer is ready, 0 means not ready.
Writing this port with a 8 bit value will set the software scrambler pattern. The data that appears on the output side will be the result of the input bus EX-ORed with this pattern, bit by bit. The software lock is a scrambler built between the CPU and external interface. The scrambling pattern is contained in port 0xFF and is not readable. CPU data output to external bus will be XORed with this pattern in a bit by bit fashion to generate the real data on external bus. By the same mechanism, data from external bus is also XORed with this pattern and read by CPU. Therefore it the external device is RAM, the software lock simply has no affect as long as the scrambling pattern remains unchanged. For I/O operation the pattern is gated to 0 and thus scrambling action is nullified, In BASIC operation the scrambling pattern is generated by a random number routine. For game cartridge the lock pattern is generated from data in the game cartridge itself.
Internal and external space definition: Any non-onboard elements will be decoded als external. Onboards elements are:
- 8K ROM
- 4K RAM
- I/O location 0xFC - oxFF
This port is 6 bits wide, when read, it returns the row data from the keyboard matrix
The keyboard is usually scanned in the following manner:
The keyboard is a 6 row by 8 column matrix. The column is connected to the higher order address bus A15-A8. When Z80 executes its input instruction sets, either the current content of the accumulator (A) or the content of register (B) will go to the higher order address bus. Therefore the keyboard can be scanned by placing a specific scanning pattern in (A) or (B) and reading the result returned on rows.
Port Initialization Procedure
- Cassette port:
Needs no initialization
- Memory Mapper:
Do not write to this bit unless block switching is desired for CP/M applications.
- Printer port:
MUST be initialized to logical 1 prior to printing.
- Software lock:
Depends on the desired function. Usually a game cartridge gains control from BASIC, at this point the lock is already prepared and does not need further intervention. Writing the software lock unintentionally simply means the program crash.